iGPU
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Posts posted by iGPU
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5 hours ago, Driftwood said:
So Im probably not going to see any improvements on mine unless I get power table DSDT and GPU water-cooling which is making you improve back to Proxmox? Actually do you mind posting your latest config for me to analyse? There may well be something I have forgotten to do. Thanks @iGPU
Did you check your debug boot log to seee if anything changed in the hex addresses for MMIO?
Here is my latest config.plist file (sans SNs). Keep in mind that I use many custom SSDTs that are not uploaded, so this config file is not plug-'n-play.
Also, I use the unpopular RadeonBoost as well as Radeon VII properties injected via the OC/DevProp section (the latter you can view in the DevProp section). I'll attach below v1.6 of RadeonBoost that I use.
Further, I've begun re-using WEG, but with the -wegbeta boot argument; the computer seems to boot more smoothly and the log-in screen is the correct resolution (not a lower resolution as without WEG). However, I do routinely set UIScale to "02" in the OC/NVRAM section.
(BTW, the above re-test of the DaVinci 2-Candle test was done with this config file set-up.)
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8 hours ago, dtek said:
The Aquantia card used to work for me but I don't know what changes I made and now it doesn't work anymore. My other 2 integrated lan cards work fine. When I plugged the ethernet cable in, there's activity light but no internet. I started from scratch and it still doesn't work, then I tested in windows and it works fine.
It is reported that Aquantia ports will stop working under macOS if their drivers are updated under Windows. Did you update the Aquantia drivers while running Windows? (This is based on info I remember from one of KGP's threads on his X299 builds.)
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On 9/8/2020 at 8:23 PM, meina222 said:
@fabiosun, @iGPU - something interesting I noticed earlier and just confirmed it's a real phenomenon.
When I flash the TR card and I immediately read the flashed ROM afterwards, and compare the SHA against the .bin file I just flashed I get a match - gives me a peace of mind flash was successful (even though it's checked by the flashrom software anyways).
But when I then install the card in the PCIE slot and run with MacOS and then take it out to read the ROM agin the SHA's no longer match! How is this possible? Does the OS modify the firmware somehow? Happened twice (with NVM23 and NVM33 images alike).
About to re-flash backt to NVM23 to test if this fixes my display not using full TB3 capability.
Edit: Maybe when I specify a unique UID in the SSDT's ROM section that gets written in the chip and alters its contents.
I think it's possible that ROM is being fiddled with. (Oh, there's pun about 'fiddling while ROM burned' hiding in there.😉)
A similar thing happens with Aquantia ethernet ports. If a mobo with Aquantia is run under Windows and Windows is used to update drivers for Aquantia, those Aquantia ports then won't work under macOS. So OS's do play with the ROM.
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On 9/8/2020 at 8:35 AM, meina222 said:
Something I missed - It seems that reason for my display only hitting 30 hz at 4K is that it runs at legacy TB speeds (TB gen 1.0) and not 3.0.
I wonder if the reason is that Z390 firmware doesn't support displays well according to:
https://www.reddit.com/r/Thunderbolt/comments/g5as92/apple_thunderbolt_display_titan_ridge_aic_z390_a/I may need to flash NVM23 after all, as I don't like this crippled display limitation.
The 40G/s only seems to appear with a proper SSDT, and only if the following is present under "Device (NHI0)":
"linkDetails",
Buffer (0x08)
{
0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00 // ........
},
If you're not certain about how to fix, upload your SSDT and I'll take a look.
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On 9/8/2020 at 5:12 PM, Driftwood said:
Big Sur Bare Metal Candle Test
(Not as Quick As Proxmox, however we are using a patched dylib library replacing BMDs own to get Davinci Resolve working under Big Sur / AMD bare metal - and AMD BM is not supported under Mac from Davinci..
But even with the patch, it's still very acceptable.
* On Proxmox I was getting apx 34fps on 66 Blur Nodes, Here around 20-24fps at moment of screen grab. Had a load of background apps going on if that didn't help.
I ran the DaVinci 2 candle tests a week or so ago and forgot to post the results. At the time, they were basically the same as your results: around 34-35 fps in VM with dual Radeon VIIs in Catalina (1 Radeon VII giving 16 fps). Meanwhile, in bare metal (Big Sur ß4) dual Radeon VIIs gave ~24 fps. (BTW, as a reference, 16 fps is a typical result when running when using one 2080 Ti in Win10.)
I re-ran the DaVinci 2-Candle test since I've now reduced the AMD kernel patches and added the custom DSDT. The 2-Candle test now returns values the same as VM, fluctuating between 32 and 36, mostly hovering about 34. So for my uses, I'm not seeing any advantage of VM over bare metal.
The screen grab was at 35 fps with 66 nodes under Big Sur ß6 bare metal, dual Radeon VIIs.
And I've repeated the C15 tests and consistently get the same results (the C15 results are same for 1 or 2 GPUs):
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3 hours ago, Ploddles said:
Yes, the system is very stable. Updating the BIOS has benefits if you have more than 1 graphics card - Above 4G can now be enabled without it hanging the system. Big Sur and Catalina now boot fine with or without Above 4G enabled. The MMIO Whitelist hasn't changed, the values obtain with the Debug are the same as with the previous BIOS version. They are also the same with or without Above 4G enabled so you don't need to make any changes for that to your config file.
You do need to make changes to the config.plist if you update to OC 0.6.1, eg you need to add the Arch - String - Any values to all your Add (kexts) and Patch sections in the Kernel part. There are a few other bit dotted throughout the rest of the config as well.
If you want I can upload my updated config.plist file and you can see and compare with yours and see where the changes are.
Many changes occurred at the end of v061, carrying over into v062. These late changes are all in the Kernel section, adding "Force" and "Scheme" sub-sections as well as an "Arch" parameter for each Add, Block, Force, and Patch sub-section entry.
At the very end of v061, a new quirk was added, DisableLinkeditJettison. This new quirk is specifically for Big Sur and should be enabled. (To quote the Docs, "This option lets Lilu.kext and possibly some others function in macOS Big Sur with best performance without keepsyms=1 boot argument.")
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15 hours ago, dtek said:
Do you by any chance use the 10g lan card that comes with the board? Mine suddenly stopped working. I don't know if it's related to MMIO whitelist editing I just made and/or the removal of SSDT. I have to revert the changes to see if it works again.
Aquantia is supported natively through Mojave (and I thought ok in Catalina), but Big Sur requires a kernel patch. The inactivation has nothing to do with SSDT or MmioWhitelist.
Pavo has provided this on another forum. Here it is below (as written this will work on HS thru BS; if you only want for Catalina-BS, change 17.0.0 to 19.0.0):
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1 hour ago, Driftwood said:
PikerAlpha used to work for Apple and stopped writing a few years ago after his wife was killed in an auto accident. (Whether he is working again for Apple, I don't know.)
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1 hour ago, dtek said:
I have an old monitor that only supports hdmi. Upgraded to the latest OC build but only sleep mode worked, shutdown/restart froze
I'm not sure how to calculate hex values for disabled 4g. I read it a few times and still didn't get it.
The linked instruction is about as lucid as you'll find on such an esoteric build. But this makes me wonder did you actually create the debug file to generate your own hex values?
Do you understand that OC comes in RELEASE and DEBUG versions, and you need to use the latter? (The link within the link, here, again, tells you how to make this file in steps A1 a + b.)
Look at the pop-up that has green/red numbers (4th spoiler) in first link (here again). Those are hex. The hex values are given in your debug text file. The white numbers in the right column are decimal. You calculate the decimals equivalent, from the hex values, derived from your debug file. (Even the built-in Mac calculator can convert; Google for other on-line calculators if you don't like that one.)
The left green/red values should be similar to those in your debug file. Look for a pattern. Your list created in the debug file should match up (as described).
Building a Hackintosh, and esp a TRX40, means having to sit and think about things on your own. Problem solving is part of building one, and will be for the life of the computer. Develop those problem solving skills now.
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1 minute ago, dtek said:
I got everything working except for shutdown and restart. How do I get this to work?
Create a correct MmioWhitelist following these directions. Once working, Shutdown should work. (There are some hardware/USB issues that could prevent Shutdown from consistently working even with a proper MmioWhitelist.)
The list is specific for your setup, so you need to do it yourself (copying other's list will rarely work unless everything is identical).
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2 hours ago, meina222 said:
@Pavo, I also get this ACPI error. Does the above apply to all boards or just MSI Creator? Thanks.
It should work on all of our mobos. Code is below to copy/paste (I added to comments to show how it is derived; data are basically ascii to hex conversions).
<key>Delete</key> <array> <dict> <key>All</key> <false/> <key>Comment</key> <string>Delete SHAKTOOH (hex=oemtab); hex SSDT=tablesig; 4271=0010AF (from "log show --last boot | grep ACPI")</string> <key>Enabled</key> <true/> <key>OemTableId</key> <data> U0hBS1RPT0g= </data> <key>TableLength</key> <integer>4271</integer> <key>TableSignature</key> <data> U1NEVA== </data> </dict> </array>
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23 minutes ago, Driftwood said:
@iGPU Gave it a whirl in Catalina: No real performance increase (slight decrease). Im getting 98fps avg on BS without DevProp, but will try it over on BS shortly.
Here's OC debug text DevProp rip which I assume success means the DevProps were loaded ok.
Ploddles post above shows overall C15 scores about like mine and even with a single RX580 (but the RX580 won't compare as well if tested in LuxMark or using in DaVinci).
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On 9/7/2020 at 11:57 AM, Ploddles said:
Thanks for taking a look. I have removed the Slide value now I have tested it and found it didn't change anything.
I followed your method on page 7 to obtain and calculate the Whitelist, it is only the last 3 or 4 values that are different from everybody else's and following the recommendations earlier I have enabled them all except the last 4.
Next thing to try is to remove all the USB devices, except the keyboard and mouse, to see if they affect Sleep. When I put it to sleep, the keyboard, mouse and monitors turn off and then the MB clicks and the BIOS output LEDs start to count up. The mouse, keyboard and monitor do not turn back on and the BIOS codes stop at 30. On a normal start/restart it counts up to AA. There is nothing in the manual about what '30' indicates and a google search wasn't fruitful.
CREATING MMIOWHITELIST
What I originally posted is unnecessarily cumbersome. There is no longer any need to test and re-boot after each modification. Instead, of re-doing the earlier post, I'll write an updated methodology here on how to make an MmioWhitelist (and link the original post to this one).
Here are the instructions in a nutshell.
First gather your debug text file, which is normally saved on the booted EFI partition. (If you're not certain how to create the debug text file, see the earlier MmioWhitelist post here.) Once you've gotten this debug text file, locate the area of interest within this file, by searching for "MMIO" as shown in the Spoiler below (an excerpt is taken from a file with a name such as "opencore-2020-08-31-150945.txt").
Excerpt from "opencore-2020-08-31-150945.txt":
SpoilerCopy and paste this section, placing in a new text file for processing and future reference:
Spoiler09:203 00:002 OCABC: MMIO devirt 0xCB100000 (0x81 pages, 0x8000000000000001) skip 1 09:206 00:002 OCABC: MMIO devirt 0xD7180000 (0x81 pages, 0x8000000000000001) skip 1 09:211 00:005 OCABC: MMIO devirt 0xE3180000 (0x81 pages, 0x8000000000000001) skip 1 09:214 00:002 OCABC: MMIO devirt 0xE3300000 (0x100 pages, 0x8000000000000001) skip 1 09:217 00:002 OCABC: MMIO devirt 0xEF100000 (0x181 pages, 0x8000000000000001) skip 1 09:222 00:005 OCABC: MMIO devirt 0xFEA00000 (0x100 pages, 0x8000000000000001) skip 1 09:225 00:002 OCABC: MMIO devirt 0xFEC00000 (0x1 pages, 0x8000000000000001) skip 1 09:228 00:002 OCABC: MMIO devirt 0xFEC10000 (0x1 pages, 0x8000000000000001) skip 1 09:233 00:005 OCABC: MMIO devirt 0xFED00000 (0x1 pages, 0x8000000000000001) skip 1 09:236 00:003 OCABC: MMIO devirt 0xFED40000 (0x5 pages, 0x8000000000000001) skip 1 09:239 00:002 OCABC: MMIO devirt 0xFED80000 (0x10 pages, 0x8000000000000001) skip 1 09:245 00:005 OCABC: MMIO devirt 0xFEDC2000 (0xE pages, 0x8000000000000001) skip 1 09:247 00:002 OCABC: MMIO devirt 0xFEDD4000 (0x2 pages, 0x8000000000000001) skip 1 09:250 00:002 OCABC: MMIO devirt 0xFEE00000 (0x100 pages, 0x8000000000000001) skip 0 09:256 00:005 OCABC: MMIO devirt 0xFF000000 (0x1000 pages, 0x8000000000000001) skip 1 09:259 00:002 OCABC: MMIO devirt 0x4040000000 (0x10400 pages, 0x8000000000000001) skip 1 09:262 00:002 OCABC: MMIO devirt 0x6F70000000 (0x10400 pages, 0x8000000000000001) skip 0 09:267 00:005 OCABC: MMIO devirt 0x9EA0000000 (0x10400 pages, 0x8000000000000001) skip 0 09:270 00:002 OCABC: MMIO devirt 0xCDD0000000 (0x10400 pages, 0x8000000000000001) skip 0From this, copy the hex values, creating the following list, which may be in the same, new text file. (I've color-coded for purposes of description; you do not need to do this step).
Spoiler0xCB100000
0xD7180000
0xE3180000
0xE33000000xEF100000
0xFEA00000
0xFEC00000
0xFEC10000
0xFED00000
0xFED40000
0xFED80000
0xFEDC2000
0xFEDD4000
0xFEE00000
0xFF0000000x4040000000
0x6F70000000
0x9EA0000000
0xCDD0000000
These are for my MSI Creator mobo with Above 4G enabled. The red values will be used; the green will not be used (don't even bother entering them into the MmioWhitelist section). That is, the bottom 4 entries do not seem to be necessary for MmioWhitelist.
*****
Clarification (5/11/21):
Vit9696, the main person behind OpenCore, recommended not using the last 4 entries. However, the most up-to-date method of creating the MMIOWhitelist suggests disabling all entries in the above Spoiler that say "skip 0" and enabling all entries that say "skip 1". This is not discussed below (it is shown in the final code example), but is probably the best method of choosing whether or not to enable or disable a given entry. The color codes have been accordingly updated.
*****
Next, run calculations for each red hex value, creating another set of data, shown in white (the decimal conversion of the adjacent hex values). The bottom 11 hex values are in common with all of our mobos. If you have Above 4G enabled, they'll be on the bottom; if not, there will be only 2 values above 0xEF10000 and 2 other values below 0xEF10000, namely 0xFA180000 and 0xFA300000 (shown in orange in the 4G Disabled section).
So there is a bit of a pattern... the differences between our mobos seem to lay in the top 4 values if Above 4G is enabled, or, the top 2 values, if Above 4G is disabled, (shown in yellow below for the MSI Creator mobo):
Spoiler4G Enabled:
0xCB100000 3406823424
0xD7180000. 3608674304
0xE3180000 3810000896
0xE3300000 38115737600xEF100000 4010803200
0xFEA00000 4271898624
0xFEC00000 4273995776
0xFEC10000 4274061312
0xFED00000 4275044352
0xFED40000 4275306496
0xFED80000 4275568640
0xFEDC2000 4275838976
0xFEDD4000 4275912704
0xFEE00000 4276092928
0xFF000000 42781900800x4040000000 275951648768
4G DISabled:
0xB2100000 2987393024
0xB3180000 3004694528
0xEF100000 4010803200
0xFA180000 4195876864
0xFA300000 4197449728
0xFEA00000 4271898624
0xFEC00000 4273995776
0xFEC10000 4274061312
0xFED00000 4275044352
0xFED40000 4275306496
0xFED80000 4275568640
0xFEDC2000 4275838976
0xFEDD4000 4275912704
0xFEE00000 4276092928
0xFF000000 42781900800x4040000000 275951648768
These values will, in turn, be entered into the MmioWhitelist section in OC (again, these are my values; yours will be somewhat different) for each fo the 15 values.
Note that all of these values will be enabled (set to "Yes"). Also note that these values are what were labelled above as "skip 1" ("skip 0" means that entry was set to "No" in MmioWhitelist).
Since we've removed the bottom 4 entries, which would otherwise have been disabled (set to "No"), all values in our new MmioWhitelist will be enabled (again, set to "Yes").
SpoilerAnd the code will look like this (Above 4G enabled):
Spoiler<key>MmioWhitelist</key> <array> <dict> <key>Address</key> <integer>3406823424</integer> <key>Comment</key> <string>MMIO devirt 0xCB100000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>3608674304</integer> <key>Comment</key> <string>MMIO devirt 0xD7180000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>3810000896</integer> <key>Comment</key> <string>MMIO devirt 0xE3180000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>3811573760</integer> <key>Comment</key> <string>MMIO devirt 0xE3300000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4010803200</integer> <key>Comment</key> <string>MMIO devirt 0xEF100000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4271898624</integer> <key>Comment</key> <string>MMIO devirt 0xFEA00000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4273995776</integer> <key>Comment</key> <string>MMIO devirt 0xFEC00000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4274061312</integer> <key>Comment</key> <string>MMIO devirt 0xFEC10000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4275044352</integer> <key>Comment</key> <string>MMIO devirt 0xFED00000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4275306496</integer> <key>Comment</key> <string>MMIO devirt 0xFED40000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4275568640</integer> <key>Comment</key> <string>MMIO devirt 0xFED80000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4275838976</integer> <key>Comment</key> <string>MMIO devirt 0xFEDC2000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4275912704</integer> <key>Comment</key> <string>MMIO devirt 0xFEDD4000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4276092928</integer> <key>Comment</key> <string>MMIO devirt 0xFEE00000</string> <key>Disabled</key> <true/> </dict> <dict> <key>Address</key> <integer>4278190080</integer> <key>Comment</key> <string>MMIO devirt 0xFF000000</string> <key>Enabled</key> <true/> </dict> <dict> <key>Address</key> <integer>275951648768</integer> <key>Comment</key> <string>MMIO devirt 0x4040000000</string> <key>Enabled</key> <true/> </dict> </array>
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31 minutes ago, Driftwood said:
@iGPU After trying the DSDT, and looking at comparable builds I am at a losss to explain your 149 fps? There must be something else you are doing or can you get down to the nitty gritty of the DSDT to find out the cause of this graphics performance in CB15? I have to O/c to 4Ghz just to get over 100fps!
I really need to understand how. You are not o/c GPU's etc..?. I know u have a decent water block setup but 50% greater than most of us is really quite stunning.
I've always added DevProper which some here don't like so I don't promote. But I've used before and after the custom DSDT file. I'll attach below as a plist file. To use, open in editor and copy/paste into your DevProp OC section. It is for dual Radeon VII in slots 1 & 3, which is what I recall you're using. These do inject some speed properties. I think they'll be okay with air-cooled. If it throttles or crashes during a stress test, let me know and I'll provide a less-energetic version. There are two sections for each GPU: one is for the display, the other for audio. The audio portion is simply descriptive.
If anyone wishes to use for 1 Radeon VII, only use the slot-1.
As far as OC, I have not. XMP is off. And none of these should much influence GPU performance. Until we trimmed the Kernel Patch list and I added the custom DSDT, my FPS were in the 60s. Now MarkLux has always been good and your values are the same as mine. So I have the feeling that your set up is just fine. (In my opinion, the tests are somewhat strange in and of themselves.)
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54 minutes ago, Ploddles said:
I finally had a chance to test the MMIOWhitelisting, disabling the last 3/4 entries but enabling all the others.
There was no difference between disabling the last 3 or 4 and the system booted fine. Shutdown and restart still work as previous. Sleep still does not work.
I also calculate my Slide value, which worked out as 80, but again, this doesn't seem to affect anything.
I cannot boot at all with Above 4G enabled and the debug version of OC does not show any MMIO values in the report.
Attached is my DSDT file to add to the collection - Gigabyte AORUS Xtreme.
I don't see anything to 'fix' on your DSDT file. Both of the GB DSDT file compile without errors and have the proper GPRW injections.
I not certain that you need to use a Slide value. I don't believe any one is using; I know I am not. It is not necessary to use Above 4G; if not working ignore it.
You do need to have a proper MMIO section, which is specific for your mobo. Show us the MmioWhitelist values and we can help you select the correct ones.
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1 hour ago, Pavo said:
Just wanted to give everyone an update on the GPU performance fix, it is 100% the last kernel patch, Fix PAT. Disable it and see if you can still boot and if you can, your GPU performance will be like it should be. Currently trying to get the AMD devs to re-work the patch so all AMD systems can benefit from it using the PAT fix without hindering the GPU performance.
I'd already removed this when reducing the patch list down to 13 total patches. The GPU performance on C15 increased from a very low 67 to 97 FPS without Fix PAT.
When I added the modified DSDT file, the GPU further increased to 140 FPS.
Did you try the modified DSDT file? It should work since we use the same mobo. I derived it with Above 4G enabled, and did not check if this setting affects the DSDT file.
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On 9/6/2020 at 5:45 PM, Driftwood said:
@iGPU Here's the Asrock TRX40 Creator (Above 4G, CSM Disabled BIOS, standard settings) DSDT file to add to your database.
Asrock Creator Above 4G no csm DSDT.zip 14.13 kB · 0 downloads
In looking it over, it has more in common with MSI than GB. However, all 3 have 90% in common with each other.
None of the other 2 mobos (GB/ASrock) have the large Windows section at the end as described above for the MSI file. The ASRock does have the same compilation errors. I'll work to remove them and upload, probably tomorrow, for you to try.
EDIT:
I cleaned up the compilations errors and added several GPRW calls that were missing (same as with MSI). Let me know how it boots.
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2 hours ago, meina222 said:
Just keep in mind that I didn’t properly extract my DSDT as I should say from Linux. It’s just what I see launching MaciASL in Big Sur. I hope the disassembler is bug-free, I should probably extract it outside of macOS.
You can extract with OC using Debug version: set DisplayDelay to 64, Target to 65 and SysReport to "Yes". This will create a SysReport folder on the EFI partition. Inside this will be a DSDT file.
I should mention that the derived DSDT file will change not only with mobo, but BIOS. So if BIOS is updated, the DSDT file manipulation must be re-done.
***
3 hours ago, fabiosun said:@iGPUtested by now your dsdt
in my case it hangs with latest two lines AppleUSBresource@ then after some seconds I have screen character corruption and stop sign
tested with 4g on and off and in different Usb ports
Send me a DSDT file based on instructions in above post. Maybe I can quickly get rid of the same compilation errors and Windows stuff.
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1 hour ago, meina222 said:
Will step away for a few hours. I cleared CMOS and will reconfigure TB from scratch (won't reflash yet) to figure how to get my display going. If there's any extra files you want me to share I will check back in a few hours. Hope you find out how to fix the USB in that DSDT!
Update: after I switched the Display Port used for the bridging cable on my 5700XT, I can now boot and have my display working in TB. Weird, I think this is a GB bug. Will happily take one port for now as I don't use 8K. So bridge from DP 1 on 5700XT to mini DP1 on TB causes BIOS 61, but if I bridge Navi's DP2 to mini DP2 it works. Oh well. Maybe this is a quirk of the 390 NVM33 ROM. I guess can't have it all perfect.
I found some interesting things and posted here.
5 minutes ago, fabiosun said:Hi know
this day I have put my card on a x299 system i see without any ssdt hs01 hs02 ss 01 and 02 maybe sp like meina i mean
usb works if connected on cold boot
i would like to reach the condition only to see that devices in usb thunderbolt three
i understand how his need maybe a dsdt job
Send me the X299 IORE file and I'll make one for you. I also have X299 system, using ASUS Prime Deluxe (1st edition).
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MSI Customized DSDT File
While working on the USB problem for Thunderbolt, which is now fully working on meina222's GB mobo, I did a comparison of the GB DSDT and the MSI Creator DSDT to see if there are power injection differences. There were, plus some other differences.
The basic differences were: a large section seemingly devoted to Windows (towards the end of the file; shown in Spoiler below) not at all present on GB, 10 fewer GPRW references on the MSI file, and some errors in 8 sections that would not compile (but were okay on GB).
SpoilerScope (_SB) { Device (WMIC) { Mutex (MWMI, 0x00) Name (_HID, "PNP0C14" /* Windows Management Instrumentation Device */) // _HID: Hardware ID Name (_UID, "WMIC") // _UID: Unique ID Name (WMIO, 0xB9B44A98) Name (WQBA, Buffer (0x06CF) { /* 0000 */ 0x46, 0x4F, 0x4D, 0x42, 0x01, 0x00, 0x00, 0x00, // FOMB.... /* 0008 */ 0xBF, 0x06, 0x00, 0x00, 0x88, 0x2B, 0x00, 0x00, // .....+.. /* 0010 */ 0x44, 0x53, 0x00, 0x01, 0x1A, 0x7D, 0xDA, 0x54, // DS...}.T /* 0018 */ 0x18, 0xD1, 0x94, 0x00, 0x01, 0x06, 0x18, 0x42, // .......B /* 0020 */ 0x10, 0x0B, 0x10, 0x0A, 0x0B, 0x21, 0x02, 0x0B, // .....!.. /* 0028 */ 0x83, 0x50, 0x3C, 0x18, 0x14, 0xA0, 0x45, 0x41, // .P<...EA /* 0030 */ 0xC8, 0x05, 0x14, 0x95, 0x02, 0x21, 0xC3, 0x02, // .....!.. /* 0038 */ 0x14, 0x0B, 0x70, 0x2E, 0x40, 0xBA, 0x00, 0xE5, // ..p.@... /* 0040 */ 0x28, 0x72, 0x0C, 0x22, 0x02, 0xF7, 0xEF, 0x0F, // (r.".... /* 0048 */ 0x31, 0x06, 0x88, 0x14, 0x40, 0x48, 0x22, 0x84, // 1...@H". /* 0050 */ 0x44, 0x00, 0x53, 0x21, 0x70, 0x84, 0xA0, 0x5F, // D.S!p.._ /* 0058 */ 0x01, 0x08, 0x1D, 0x0A, 0x90, 0x29, 0xC0, 0xA0, // .....).. /* 0060 */ 0x00, 0xA7, 0x08, 0x22, 0x68, 0x73, 0x02, 0x32, // ..."hs.2 /* 0068 */ 0x0D, 0x25, 0xA0, 0xC2, 0x31, 0x84, 0xD4, 0xF2, // .%..1... /* 0070 */ 0x1C, 0xA4, 0x1D, 0x49, 0x83, 0x88, 0x92, 0xC0, // ...I.... /* 0078 */ 0x02, 0x47, 0x80, 0x12, 0x33, 0x02, 0x94, 0x4E, // .G..3..N /* 0080 */ 0x64, 0xC1, 0xB7, 0x88, 0x2C, 0xA1, 0x28, 0x9A, // d...,.(. /* 0088 */ 0x44, 0x94, 0x04, 0xD1, 0xFB, 0x46, 0xD0, 0x90, // D....F.. /* 0090 */ 0xCA, 0x15, 0xE0, 0x5D, 0x80, 0xED, 0x11, 0x88, // ...].... /* 0098 */ 0xC0, 0xF0, 0x3C, 0xA6, 0x09, 0x10, 0x16, 0x63, // ..<....c /* 00A0 */ 0x89, 0x0A, 0xE1, 0x00, 0x06, 0xE3, 0x01, 0x44, // .......D /* 00A8 */ 0x72, 0x86, 0x89, 0x02, 0xB6, 0xD7, 0x69, 0xC8, // r.....i. /* 00B0 */ 0xE4, 0x18, 0xA9, 0x24, 0x38, 0xD4, 0x08, 0x3D, // ...$8..= /* 00B8 */ 0xCA, 0xE6, 0x05, 0xE8, 0x1E, 0xAC, 0x06, 0xE2, // ........ /* 00C0 */ 0x91, 0x85, 0x64, 0xD2, 0x86, 0x82, 0x1A, 0xB6, // ..d..... /* 00C8 */ 0x27, 0x75, 0x4A, 0x9E, 0xA1, 0x25, 0x0F, 0x92, // 'uJ..%.. /* 00D0 */ 0x10, 0x78, 0x14, 0x0C, 0x8D, 0x13, 0x94, 0x05, // .x...... /* 00D8 */ 0xA1, 0x1D, 0xD1, 0x61, 0x12, 0xC0, 0x93, 0xF0, // ...a.... /* 00E0 */ 0x0C, 0x8B, 0x1F, 0xB2, 0xA0, 0x4F, 0xE4, 0xAC, // .....O.. /* 00E8 */ 0x0F, 0x98, 0x1D, 0x07, 0x7C, 0x04, 0xC0, 0xC1, // ....|... /* 00F0 */ 0x1A, 0x28, 0x5C, 0xC0, 0xF3, 0x39, 0x86, 0xC8, // .(\..9.. /* 00F8 */ 0x71, 0x0F, 0x36, 0xC6, 0x51, 0x44, 0x4E, 0x50, // q.6.QDNP /* 0100 */ 0xE1, 0x44, 0xE4, 0x73, 0xD2, 0x12, 0x74, 0x04, // .D.s..t. /* 0108 */ 0x20, 0x60, 0xD1, 0x0C, 0xD6, 0x33, 0x38, 0x91, // `...38. /* 0110 */ 0x3D, 0x02, 0x94, 0x0C, 0x08, 0x79, 0x14, 0x60, // =....y.` /* 0118 */ 0x55, 0xC0, 0xFF, 0x1F, 0xF7, 0x34, 0x4C, 0xD0, // U....4L. /* 0120 */ 0xBD, 0x00, 0x65, 0x02, 0x8C, 0x09, 0x70, 0x06, // ..e...p. /* 0128 */ 0x2D, 0x6F, 0x02, 0xC4, 0x41, 0x68, 0x1A, 0x6D, // -o..Ah.m /* 0130 */ 0x09, 0xB0, 0x76, 0x5B, 0xD0, 0xFC, 0x62, 0x44, // ..v[..bD /* 0138 */ 0x39, 0xCF, 0x48, 0x01, 0xC3, 0x44, 0x69, 0x0E, // 9.H..Di. /* 0140 */ 0x51, 0x58, 0x11, 0xA3, 0xC4, 0xA9, 0x19, 0x4C, // QX.....L /* 0148 */ 0x10, 0x0F, 0x0C, 0xD1, 0x22, 0x85, 0x65, 0x13, // ....".e. /* 0150 */ 0x08, 0xD2, 0xFE, 0x20, 0xC8, 0xA0, 0x71, 0xA3, // ... ..q. /* 0158 */ 0xF7, 0x5D, 0xE1, 0xC0, 0x8E, 0xE2, 0xE8, 0x8F, // .]...... /* 0160 */ 0xE8, 0x28, 0xD9, 0x94, 0x0F, 0xEC, 0xC9, 0x20, // .(..... /* 0168 */ 0xF4, 0xB1, 0x46, 0x8D, 0x71, 0x16, 0x09, 0x1C, // ..F.q... /* 0170 */ 0x7F, 0xA9, 0x3A, 0x50, 0x38, 0x12, 0x3C, 0xEA, // ..:P8.<. /* 0178 */ 0xAC, 0xE0, 0x73, 0x81, 0x87, 0x76, 0xD0, 0x9E, // ..s..v.. /* 0180 */ 0xE3, 0x09, 0x04, 0x79, 0x6C, 0xF0, 0x79, 0xE1, // ...yl.y. /* 0188 */ 0x81, 0xC0, 0x63, 0x60, 0xB7, 0x09, 0x1F, 0x01, // ..c`.... /* 0190 */ 0x7C, 0x42, 0xC0, 0xBB, 0x06, 0xD4, 0xD5, 0xE0, // |B...... /* 0198 */ 0xC1, 0x80, 0x0D, 0x3A, 0x1C, 0x66, 0xBC, 0x1E, // ...:.f.. /* 01A0 */ 0x7E, 0xB8, 0x13, 0x38, 0xB9, 0x87, 0x0B, 0x7E, // ~..8...~ /* 01A8 */ 0xD0, 0xF0, 0xE0, 0x70, 0x77, 0x88, 0x93, 0x39, // ...pw..9 /* 01B0 */ 0xB2, 0x52, 0x05, 0x98, 0x3D, 0x1C, 0xE8, 0x18, // .R..=... /* 01B8 */ 0xE1, 0x93, 0x06, 0x3B, 0x03, 0x60, 0xE4, 0x0F, // ...;.`.. /* 01C0 */ 0x02, 0x35, 0x32, 0x43, 0xFB, 0x44, 0xF1, 0xC2, // .52C.D.. /* 01C8 */ 0x61, 0xC8, 0xE7, 0x84, 0xC3, 0x62, 0x62, 0x4F, // a....bbO /* 01D0 */ 0x1C, 0x74, 0x3C, 0xE0, 0xBF, 0x08, 0x3C, 0x65, // .t<...<e /* 01D8 */ 0x78, 0xFA, 0x9E, 0xAF, 0x4F, 0x21, 0xE0, 0xC1, // x...O!.. /* 01E0 */ 0x38, 0x83, 0x50, 0x0F, 0x0D, 0xAF, 0x0D, 0x9E, // 8.P..... /* 01E8 */ 0xDF, 0x3B, 0x03, 0xFE, 0x14, 0xC2, 0xFF, 0xFF, // .;...... /* 01F0 */ 0xA7, 0x10, 0xF0, 0xE2, 0x1D, 0x00, 0xE6, 0x38, // .......8 /* 01F8 */ 0xE0, 0x01, 0x70, 0xF0, 0xA7, 0x88, 0xB3, 0xB3, // ..p..... /* 0200 */ 0xD2, 0x39, 0x21, 0x4F, 0x2A, 0x60, 0x10, 0xA6, // .9!O*`.. /* 0208 */ 0x61, 0xEC, 0x2C, 0x28, 0x85, 0x6C, 0x2C, 0xDE, // a.,(.l,. /* 0210 */ 0xC3, 0xA7, 0x42, 0x80, 0x74, 0xB4, 0x38, 0x3E, // ..B.t.8> /* 0218 */ 0x4F, 0x11, 0x1E, 0xC1, 0xE0, 0xC7, 0x07, 0x9D, // O....... /* 0220 */ 0x3C, 0x3C, 0x00, 0x47, 0x26, 0x51, 0xE8, 0x41, // <<.G&Q.A /* 0228 */ 0xD1, 0xD3, 0x0A, 0x39, 0x80, 0x50, 0x10, 0x03, // ...9.P.. /* 0230 */ 0x3A, 0xC3, 0x39, 0x02, 0xAD, 0xE2, 0x1C, 0x41, // :.9....A /* 0238 */ 0xE6, 0x70, 0x14, 0xA7, 0x99, 0xA0, 0xE8, 0x2B, // .p.....+ /* 0240 */ 0x04, 0x9D, 0xB4, 0x2F, 0x07, 0x7C, 0x59, 0x1A, // .../.|Y. /* 0248 */ 0x0B, 0x01, 0xB6, 0x9A, 0xCB, 0x09, 0x0A, 0xCC, // ........ /* 0250 */ 0xF7, 0x0F, 0x4E, 0x50, 0xD7, 0x01, 0x02, 0x64, // ..NP...d /* 0258 */ 0xFA, 0x2E, 0x08, 0xA0, 0x00, 0xF2, 0x89, 0xC0, // ........ /* 0260 */ 0x57, 0x80, 0x97, 0x02, 0x36, 0x86, 0xB7, 0x00, // W...6... /* 0268 */ 0xA3, 0x19, 0x9D, 0x87, 0x1F, 0x2A, 0x2A, 0xEE, // .....**. /* 0270 */ 0x50, 0x29, 0x88, 0x87, 0xEA, 0x28, 0x43, 0x45, // P)...(CE /* 0278 */ 0xCF, 0xC4, 0xC7, 0x09, 0xCF, 0xA8, 0x75, 0x10, // ......u. /* 0280 */ 0xCD, 0xD1, 0x04, 0xAF, 0x04, 0x09, 0xFE, 0xFF, // ........ /* 0288 */ 0x8F, 0x1F, 0x70, 0x6E, 0x02, 0x21, 0x9F, 0x42, // ..pn.!.B /* 0290 */ 0x3C, 0x0D, 0xC3, 0x79, 0xB2, 0x1C, 0xCE, 0x93, // <..y.... /* 0298 */ 0xE5, 0x63, 0xF1, 0xE9, 0x03, 0x7C, 0xA7, 0x09, // .c...|.. /* 02A0 */ 0xDC, 0x6C, 0xC1, 0x08, 0x8F, 0x89, 0x35, 0x2A, // .l....5* /* 02A8 */ 0x7A, 0x00, 0xF2, 0xF0, 0xF8, 0xE5, 0xC0, 0xF3, // z....... /* 02B0 */ 0x79, 0x42, 0x38, 0xCA, 0x47, 0x0F, 0x5F, 0x5B, // yB8.G._[ /* 02B8 */ 0x3C, 0x9B, 0xB7, 0x04, 0xDF, 0x44, 0x3C, 0x44, // <....D<D /* 02C0 */ 0x9F, 0x85, 0x60, 0x4D, 0xE4, 0xA4, 0x7D, 0x5B, // ..`M..}[ /* 02C8 */ 0x38, 0xD9, 0xA0, 0xF1, 0xC3, 0x7A, 0x98, 0x9E, // 8....z.. /* 02D0 */ 0xD3, 0xB3, 0x10, 0x58, 0x8E, 0x15, 0xEC, 0x66, // ...X...f /* 02D8 */ 0xF1, 0x34, 0x84, 0xB9, 0x1C, 0xF9, 0x5C, 0x81, // .4....\. /* 02E0 */ 0x15, 0xBB, 0x1A, 0x1D, 0x32, 0x70, 0x61, 0xDE, // ....2pa. /* 02E8 */ 0x05, 0xBA, 0x60, 0xB0, 0x43, 0x06, 0x4C, 0xF1, // ..`.C.L. /* 02F0 */ 0x90, 0x3A, 0x64, 0x70, 0xD9, 0x14, 0x12, 0x4E, // .:dp...N /* 02F8 */ 0xA3, 0xA3, 0x02, 0x97, 0x7A, 0xD6, 0xA0, 0x20, // ....z.. /* 0300 */ 0x1E, 0xA4, 0x0F, 0x19, 0xE0, 0xFF, 0xFF, 0x1F, // ........ /* 0308 */ 0x32, 0x80, 0x45, 0x88, 0x19, 0xA1, 0x6F, 0x3A, // 2.E...o: /* 0310 */ 0xD6, 0x7A, 0x57, 0x22, 0x57, 0x88, 0x07, 0x15, // .zW"W... /* 0318 */ 0x0F, 0x09, 0xAC, 0x43, 0xF5, 0x31, 0x04, 0xF0, // ...C.1.. /* 0320 */ 0x3D, 0x12, 0x1F, 0x43, 0x80, 0xEB, 0xFF, 0xFF, // =..C.... /* 0328 */ 0x18, 0x02, 0x3C, 0x87, 0xE9, 0x63, 0x08, 0x78, // ..<..c.x /* 0330 */ 0x2E, 0x1D, 0xEC, 0x18, 0x02, 0x3B, 0xDC, 0x19, // .....;.. /* 0338 */ 0x91, 0x86, 0x78, 0x17, 0x28, 0xC2, 0x82, 0x28, // ..x.(..( /* 0340 */ 0x8C, 0xCF, 0x88, 0x80, 0xA3, 0xF3, 0x18, 0xFE, // ........ /* 0348 */ 0x8C, 0x08, 0xF3, 0x38, 0xC6, 0x06, 0x7C, 0xC6, // ...8..|. /* 0350 */ 0xC1, 0x70, 0x47, 0x44, 0xD8, 0x97, 0xC2, 0xF7, // .pGD.... /* 0358 */ 0xC2, 0x47, 0xC4, 0x23, 0x7C, 0x77, 0xB3, 0x36, // .G.#|w.6 /* 0360 */ 0x04, 0x5D, 0x0D, 0x83, 0xC4, 0x89, 0xF0, 0x66, // .].....f /* 0368 */ 0xF8, 0x88, 0x68, 0xB8, 0x77, 0xB8, 0x47, 0x44, // ..h.w.GD /* 0370 */ 0x63, 0x04, 0x0C, 0x73, 0x34, 0xFF, 0xFF, 0x28, // c..s4..( /* 0378 */ 0x4F, 0x87, 0x41, 0x22, 0xFB, 0xA2, 0xF8, 0x7C, // O.A"...| /* 0380 */ 0x18, 0xE1, 0x75, 0xD1, 0x38, 0x0F, 0x85, 0x21, // ..u.8..! /* 0388 */ 0x1E, 0x11, 0x01, 0x3E, 0x9E, 0x19, 0xD8, 0x95, // ...>.... /* 0390 */ 0x01, 0x7B, 0x44, 0x04, 0x06, 0xFF, 0xFF, 0x23, // .{D....# /* 0398 */ 0x22, 0xF0, 0x11, 0x74, 0x44, 0xA4, 0x21, 0x8F, // "..tD.!. /* 03A0 */ 0x88, 0xA8, 0x61, 0x58, 0xC6, 0x11, 0x11, 0x35, // ..aX...5 /* 03A8 */ 0x45, 0x38, 0x27, 0x44, 0x80, 0x77, 0xFF, 0xFF, // E8'D.w.. /* 03B0 */ 0xB3, 0x14, 0xF0, 0x0E, 0x75, 0x96, 0x02, 0x6A, // ....u..j /* 03B8 */ 0x90, 0x16, 0x79, 0x42, 0x04, 0xE1, 0x59, 0x08, // ..yB..Y. /* 03C0 */ 0x96, 0xD0, 0x03, 0x22, 0xEA, 0x08, 0xE0, 0x28, // ..."...( /* 03C8 */ 0x07, 0x44, 0xD4, 0x11, 0x03, 0xCE, 0xF9, 0x10, // .D...... /* 03D0 */ 0xF0, 0xF5, 0xFF, 0x3F, 0x1F, 0x02, 0x3C, 0x3E, // ...?..<> /* 03D8 */ 0x84, 0x80, 0xF7, 0xFF, 0x7F, 0x08, 0x01, 0x87, // ........ /* 03E0 */ 0x84, 0x43, 0x08, 0xA8, 0xCE, 0x87, 0x98, 0x43, // .C.....C /* 03E8 */ 0x08, 0xAC, 0xB0, 0x3E, 0x46, 0xC0, 0x62, 0x3C, // ...>F.b< /* 03F0 */ 0x0B, 0x14, 0x63, 0x3D, 0x14, 0xC6, 0xC7, 0x43, // ..c=...C /* 03F8 */ 0xC0, 0xD1, 0xE1, 0x0C, 0x77, 0x3C, 0x84, 0x7D, // ....w<.} /* 0400 */ 0xBC, 0xE4, 0x43, 0x39, 0xB1, 0x88, 0x11, 0x1E, // ..C9.... /* 0408 */ 0xC6, 0xA2, 0xC5, 0x7C, 0x06, 0xF0, 0xF9, 0x10, // ...|.... /* 0410 */ 0xF6, 0xDD, 0xF0, 0x71, 0xF0, 0x05, 0x22, 0xC6, // ...q..". /* 0418 */ 0xB3, 0xE1, 0xC3, 0xA1, 0xCF, 0x84, 0xEF, 0x85, // ........ /* 0420 */ 0xE7, 0x11, 0xE5, 0xB9, 0xF0, 0xF9, 0x90, 0x1D, // ........ /* 0428 */ 0xE0, 0xCE, 0x21, 0x8A, 0x41, 0x22, 0x1D, 0x43, // ..!.A".C /* 0430 */ 0xD4, 0x28, 0xCF, 0x8A, 0x61, 0xC3, 0xBC, 0x0D, // .(..a... /* 0438 */ 0x86, 0x0B, 0x11, 0x29, 0x42, 0xE4, 0x88, 0x0F, // ...)B... /* 0440 */ 0x89, 0x61, 0x9E, 0x0F, 0xC1, 0xF4, 0xFF, 0x3F, // .a.....? /* 0448 */ 0x1F, 0xE2, 0x5F, 0x18, 0x3E, 0x1F, 0x02, 0x1C, // .._.>... /* 0450 */ 0x39, 0x74, 0xE0, 0xCE, 0x87, 0x60, 0xB8, 0xAA, // 9t...`.. /* 0458 */ 0xB3, 0x3B, 0x03, 0x8C, 0x03, 0x22, 0x60, 0xE0, // .;..."`. /* 0460 */ 0xFF, 0x7F, 0x40, 0xC4, 0x8B, 0x5B, 0xB7, 0x0E, // ..@..[.. /* 0468 */ 0x2B, 0x56, 0x7C, 0xDC, 0x42, 0x67, 0x79, 0x01, // +V|.Bgy. /* 0470 */ 0x08, 0xFA, 0xE8, 0x0E, 0xC7, 0x03, 0x3E, 0x45, // ......>E /* 0478 */ 0x18, 0xEA, 0x8F, 0x5B, 0x28, 0xDD, 0x14, 0x52, // ...[(..R /* 0480 */ 0x7E, 0xDC, 0x42, 0x69, 0x3D, 0x6E, 0x51, 0x10, // ~.Bi=nQ. /* 0488 */ 0x9F, 0x1C, 0x1C, 0xE3, 0x48, 0x04, 0x65, 0x66, // ....H.ef /* 0490 */ 0x4F, 0x44, 0xBE, 0x15, 0xF8, 0x64, 0xE3, 0xFB, // OD...d.. /* 0498 */ 0x16, 0x30, 0x8D, 0x30, 0x26, 0x34, 0x8C, 0xCF, // .0.0&4.. /* 04A0 */ 0x03, 0x67, 0x74, 0x9A, 0xAF, 0x5B, 0x80, 0xE5, // .gt..[.. /* 04A8 */ 0xFF, 0xFF, 0x75, 0x0B, 0x30, 0x18, 0xEE, 0xBA, // ..u.0... /* 04B0 */ 0x05, 0xD4, 0x4E, 0x00, 0xBE, 0xC0, 0xF8, 0xBA, // ..N..... /* 04B8 */ 0x05, 0xAE, 0x9B, 0x07, 0xE6, 0x82, 0x8F, 0x43, // .......C /* 04C0 */ 0x7D, 0xF9, 0xC0, 0x5F, 0x44, 0xE0, 0x9C, 0x4E, // }.._D..N /* 04C8 */ 0x1E, 0xA6, 0x0C, 0xF8, 0xEA, 0x02, 0xE7, 0x22, // ......." /* 04D0 */ 0x02, 0xAC, 0xFE, 0xFF, 0x17, 0x11, 0x80, 0xFF, // ........ /* 04D8 */ 0xFF, 0xFF, 0x8B, 0x08, 0xF0, 0x1F, 0xA6, 0x2F, // ......./ /* 04E0 */ 0x22, 0xE0, 0xBB, 0x79, 0xF0, 0x83, 0x08, 0x6C, // "..y...l /* 04E8 */ 0x82, 0xC9, 0x4E, 0xF4, 0xA8, 0x01, 0x5B, 0x01, // ..N...[. /* 04F0 */ 0x90, 0xC6, 0x7B, 0x48, 0xF1, 0x5E, 0xF9, 0xD8, // ..{H.^.. /* 04F8 */ 0xB9, 0x2E, 0xC1, 0xE4, 0xC7, 0x79, 0x54, 0x66, // .....yTf /* 0500 */ 0x12, 0xA5, 0x3E, 0x29, 0xA0, 0x72, 0x9E, 0x14, // ..>).r.. /* 0508 */ 0x28, 0x88, 0x01, 0x7D, 0xF5, 0x05, 0x56, 0xD7, // (..}..V. /* 0510 */ 0x79, 0x60, 0xFF, 0xFF, 0xBF, 0xCE, 0x03, 0xC6, // y`...... /* 0518 */ 0xE3, 0x5C, 0xE7, 0x81, 0x9E, 0xBC, 0x3B, 0x06, // .\....;. /* 0520 */ 0x68, 0xAE, 0x14, 0xEC, 0x5F, 0xF1, 0x4C, 0x81, // h..._.L. /* 0528 */ 0x21, 0x98, 0xEE, 0x72, 0x81, 0xBA, 0xE0, 0x5A, // !..r...Z /* 0530 */ 0xC3, 0xE5, 0x02, 0x71, 0xDA, 0x08, 0x7D, 0x5C, // ...q..}\ /* 0538 */ 0x6F, 0x17, 0xC0, 0xE8, 0xFF, 0x7F, 0xBB, 0x00, // o....... /* 0540 */ 0x78, 0x1A, 0xE8, 0x76, 0x01, 0xB4, 0xFE, 0xFF, // x..v.... /* 0548 */ 0x07, 0x75, 0x7E, 0xA4, 0xC5, 0xDF, 0x2E, 0xE0, // .u~..... /* 0550 */ 0x1F, 0x2A, 0xB0, 0x67, 0x62, 0xBD, 0x9E, 0x7D, // .*.gb..} /* 0558 */ 0x46, 0xA7, 0x21, 0x8E, 0xE9, 0x80, 0xD6, 0xAB, // F.!..... /* 0560 */ 0x89, 0x4F, 0xCF, 0x9E, 0x6F, 0x44, 0x9F, 0xC7, // .O..oD.. /* 0568 */ 0xC3, 0x3C, 0x3D, 0x1C, 0xF1, 0xDB, 0x83, 0x8F, // .<=..... /* 0570 */ 0xE9, 0xF0, 0xCF, 0xE6, 0x6F, 0xE5, 0x71, 0xDF, // ....o.q. /* 0578 */ 0xCF, 0x7D, 0x31, 0x7F, 0x38, 0x7F, 0x3D, 0xF7, // .}1.8.=. /* 0580 */ 0xE5, 0xDC, 0x87, 0x74, 0xA3, 0x18, 0xC6, 0x50, // ...t...P /* 0588 */ 0x86, 0x08, 0x18, 0x34, 0x56, 0x94, 0x23, 0x89, // ...4V.#. /* 0590 */ 0x69, 0x94, 0x10, 0x11, 0x5E, 0xD5, 0x8D, 0x15, // i...^... /* 0598 */ 0xD2, 0xD6, 0x8E, 0xE9, 0xA0, 0x8E, 0xBF, 0x54, // .......T /* 05A0 */ 0x1D, 0xD3, 0xE1, 0xFC, 0xFF, 0x8F, 0xE9, 0x00, // ........ /* 05A8 */ 0x1F, 0xCE, 0x0C, 0xB8, 0x63, 0x3A, 0xFC, 0x43, // ....c:.C /* 05B0 */ 0x03, 0xBF, 0x33, 0xE0, 0x4F, 0xE9, 0x80, 0x8F, // ..3.O... /* 05B8 */ 0xC0, 0x77, 0x27, 0x1A, 0x96, 0x42, 0xF7, 0x28, // .w'..B.( /* 05C0 */ 0x3E, 0x2C, 0x0B, 0x02, 0xD2, 0xFF, 0x7F, 0x84, // >,...... /* 05C8 */ 0xF0, 0x44, 0x40, 0x53, 0x08, 0xC7, 0x3F, 0x0E, // .D@S..?. /* 05D0 */ 0x01, 0x7D, 0x02, 0x1F, 0x87, 0x80, 0xF7, 0xE1, // .}...... /* 05D8 */ 0xC3, 0xF7, 0x68, 0xE0, 0x76, 0x9E, 0x01, 0x0E, // ..h.v... /* 05E0 */ 0x0A, 0x6D, 0xFA, 0xD4, 0x68, 0xD4, 0xAA, 0x41, // .m..h..A /* 05E8 */ 0x99, 0x1A, 0x65, 0x1A, 0xD4, 0xEA, 0x53, 0xA9, // ..e...S. /* 05F0 */ 0x31, 0x63, 0xDA, 0xA0, 0x24, 0xE9, 0x80, 0x40, // 1c..$..@ /* 05F8 */ 0x45, 0x2C, 0x49, 0x63, 0x72, 0x04, 0x10, 0xAA, // E,Icr... /* 0600 */ 0xEB, 0xC5, 0x22, 0x23, 0x20, 0x12, 0x09, 0x22, // .."# .." /* 0608 */ 0x20, 0xFF, 0xFF, 0x05, 0x7D, 0xD2, 0x04, 0x64, // ...}..d /* 0610 */ 0x79, 0x20, 0x02, 0x72, 0xFE, 0xC7, 0x91, 0x80, // y .r.... /* 0618 */ 0x2C, 0x66, 0x55, 0x02, 0x72, 0x06, 0x10, 0x01, // ,fU.r... /* 0620 */ 0x39, 0x10, 0x10, 0x15, 0x6F, 0x02, 0x88, 0x45, // 9...o..E /* 0628 */ 0x01, 0x11, 0x90, 0x83, 0xAB, 0x18, 0x0A, 0x0B, // ........ /* 0630 */ 0xFA, 0x1E, 0x11, 0x90, 0x65, 0xDA, 0x00, 0x61, // ....e..a /* 0638 */ 0xC9, 0x75, 0x80, 0x32, 0x19, 0x3E, 0x80, 0x58, // .u.2.>.X /* 0640 */ 0x64, 0x10, 0x01, 0xF9, 0x4D, 0x60, 0x20, 0xA7, // d...M` . /* 0648 */ 0xA3, 0x11, 0x90, 0xA3, 0x52, 0x08, 0xC8, 0x0A, // ....R... /* 0650 */ 0x95, 0x00, 0x31, 0xB9, 0x20, 0x02, 0xB2, 0x34, // ..1. ..4 /* 0658 */ 0x27, 0x40, 0x4C, 0x28, 0x88, 0x80, 0x1C, 0xEA, // '@L(.... /* 0660 */ 0xB9, 0xA4, 0xA1, 0x38, 0x86, 0x16, 0x20, 0x26, // ...8.. & /* 0668 */ 0xC2, 0x0B, 0x08, 0x0B, 0xB7, 0x7A, 0x81, 0x3A, // .....z.: /* 0670 */ 0x29, 0x88, 0xEE, 0x83, 0xC4, 0x0C, 0x10, 0xD3, // )....... /* 0678 */ 0x0A, 0xA2, 0xC1, 0x92, 0xFF, 0x9D, 0x80, 0xAC, // ........ /* 0680 */ 0x12, 0x44, 0x40, 0x56, 0xF3, 0x92, 0x10, 0x90, // .D@V.... /* 0688 */ 0xA5, 0x81, 0x08, 0xC8, 0x79, 0x80, 0x68, 0x38, // ....y.h8 /* 0690 */ 0x20, 0x1A, 0xC4, 0x0E, 0x10, 0x8B, 0x05, 0x22, // ......" /* 0698 */ 0x20, 0xCB, 0xF6, 0x03, 0xC4, 0x32, 0x80, 0x08, // ....2.. /* 06A0 */ 0xC8, 0x7A, 0x0F, 0x20, 0x02, 0xB2, 0x7A, 0x10, // .z. ..z. /* 06A8 */ 0x01, 0x59, 0x91, 0xA2, 0x03, 0x00, 0x05, 0x11, // .Y...... /* 06B0 */ 0x90, 0xA5, 0x38, 0x02, 0x62, 0xC2, 0x40, 0x04, // ..8.b.@. /* 06B8 */ 0xE4, 0x00, 0x0F, 0x2D, 0x0D, 0xCF, 0x92, 0x35, // ...-...5 /* 06C0 */ 0x01, 0xB1, 0xC0, 0x20, 0x34, 0x86, 0x28, 0x50, // ... 4.(P /* 06C8 */ 0x16, 0x0A, 0x44, 0x40, 0xFE, 0xFF, 0x03 // ..D@... }) OperationRegion (DEB1, SystemIO, 0x80, 0x04) Field (DEB1, DWordAcc, NoLock, Preserve) { DBGD, 32 } OperationRegion (SMI0, SystemIO, LSMB, One) Field (SMI0, ByteAcc, NoLock, Preserve) { APMC, 8 } OperationRegion (WMIM, SystemMemory, WMIO, WMSZ) Field (WMIM, AnyAcc, NoLock, Preserve) { CMD, 8, ERR, 32, PAR0, 32, PAR1, 32, PAR2, 32, PAR3, 32 } Field (WMIM, AnyAcc, NoLock, Preserve) { Offset (0x15), DBGM, 800, RTSM, 800 } Name (_WDG, Buffer (0x64) { /* 0000 */ 0x21, 0x12, 0x90, 0x05, 0x66, 0xD5, 0xD1, 0x11, // !...f... /* 0008 */ 0xB2, 0xF0, 0x00, 0xA0, 0xC9, 0x06, 0x29, 0x10, // ......). /* 0010 */ 0x42, 0x41, 0x01, 0x00, 0x7C, 0x78, 0x3E, 0x21, // BA..|x>! /* 0018 */ 0xD5, 0x50, 0x2D, 0x47, 0x9E, 0x08, 0xDF, 0x4F, // .P-G...O /* 0020 */ 0xB2, 0x05, 0x0D, 0x15, 0x47, 0x49, 0x02, 0x02, // ....GI.. /* 0028 */ 0x66, 0xEA, 0x34, 0xF8, 0x42, 0xA4, 0xBD, 0x48, // f.4.B..H /* 0030 */ 0xBE, 0x8C, 0x18, 0x83, 0x75, 0x57, 0xC8, 0x98, // ....uW.. /* 0038 */ 0x47, 0x42, 0x01, 0x02, 0x27, 0x24, 0x06, 0x68, // GB..'$.h /* 0040 */ 0x32, 0xC4, 0xA2, 0x4B, 0xB3, 0xD8, 0xF6, 0x39, // 2..K...9 /* 0048 */ 0x49, 0xDD, 0x7A, 0x19, 0x53, 0x50, 0x03, 0x02, // I.z.SP.. /* 0050 */ 0x38, 0x27, 0xAA, 0x81, 0xBA, 0x49, 0x98, 0x44, // 8'...I.D /* 0058 */ 0x82, 0x1B, 0xD3, 0x8B, 0x88, 0xD8, 0x14, 0x95, // ........ /* 0060 */ 0x4C, 0x44, 0x01, 0x02 // LD.. }) Method (TSTD, 1, NotSerialized) { Local0 = Zero Local1 = 0x00030D40 While ((Local0 < Local1)) { DBGD = Arg0 Local0++ } Return (Zero) } Mutex (MSMI, 0x07) Method (SMI, 5, NotSerialized) { Acquire (MSMI, 0xFFFF) CMD = Arg0 PAR0 = Arg1 PAR1 = Arg2 PAR2 = Arg3 PAR3 = Arg4 APMC = AISV /* \AISV */ While ((ERR == One)) { Sleep (0x64) APMC = AISV /* \AISV */ } Local0 = PAR0 /* \_SB_.WMIC.PAR0 */ Release (MSMI) Return (Local0) } Method (WMII, 2, NotSerialized) { Return (SMI (0x10, Arg0, Arg1, Zero, Zero)) } Method (WMIP, 2, NotSerialized) { Return (SMI (0x20, Arg0, Arg1, Zero, Zero)) } Method (WMGI, 3, NotSerialized) { If ((Acquire (MWMI, 0xFFFF) == Zero)) { DBGM = Arg2 Local0 = WMII (Arg1, Zero) Release (MWMI) } Return (RTSM) /* \_SB_.WMIC.RTSM */ } Method (WMGB, 3, NotSerialized) { If ((Acquire (MWMI, 0xFFFF) == Zero)) { DBGM = Arg2 Local0 = WMII (Arg1, Zero) Release (MWMI) } Return (RTSM) /* \_SB_.WMIC.RTSM */ } Method (WMSP, 3, NotSerialized) { If ((Acquire (MWMI, 0xFFFF) == Zero)) { DBGM = Arg2 Local0 = WMIP (Arg1, Zero) Release (MWMI) } Return (RTSM) /* \_SB_.WMIC.RTSM */ } Method (WMLD, 3, NotSerialized) { Acquire (MWMI, 0xFFFF) Local1 = WMII (0xFF, Zero) Release (MWMI) Return (RTSM) /* \_SB_.WMIC.RTSM */ } } } OperationRegion (SWBA, SystemIO, 0xB2, One) Field (SWBA, ByteAcc, NoLock, Preserve) { BASP, 8 } OperationRegion (BASG, SystemMemory, 0xFDAE04E0, 0x04) Field (BASG, AnyAcc, NoLock, Preserve) { , 1, BADA, 1, Offset (0x04) } Scope (_GPE) { Method (_E24, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF { Local0 = (BADA & 0x02) If ((Local0 == 0x02)){} Else { BASP = OBGA /* \OBGA */ } } } Scope (_SB.PCI0) { Name (SLIC, Buffer (0x9E) { "375016749376Genuine NVIDIA Certified SLI Ready Motherboard for MSI TEMP KEY 71EA-Copyright 2019 NVIDIA Corporation All Rights Reserved-274100472652(R)" }) Device (WMI1) { Name (_HID, "PNP0C14" /* Windows Management Instrumentation Device */) // _HID: Hardware ID Name (_UID, "MXM2") // _UID: Unique ID Name (_WDG, Buffer (0x14) { /* 0000 */ 0x3C, 0x5C, 0xCB, 0xF6, 0xAE, 0x9C, 0xBD, 0x4E, // <\.....N /* 0008 */ 0xB5, 0x77, 0x93, 0x1E, 0xA3, 0x2A, 0x2C, 0xC0, // .w...*,. /* 0010 */ 0x4D, 0x58, 0x01, 0x02 // MX.. }) Method (WMMX, 3, NotSerialized) { CreateDWordField (Arg2, Zero, FUNC) If ((FUNC == 0x41494C53)) { Return (SLIC) /* \_SB_.PCI0.SLIC */ } Return (Zero) } } }
After removing the Windows section and applying the other fixes, I came up with a customized DSDT file. It booted easily with no apparent issues. (Note: if you're not booting into Windows via OC, this customized DSDT file won't matter. Boot into Windows from BIOS and this DSDT modified file will have zeros influence.)
I believe this customized DSDT file will work on all MSI (and maybe even most TRX40, but I don't know as I cannot test; note: no GB user should use as it is a derivative). The customized DSDT file is attached below. When derived for my MSI, I did have Above 4G enabled; I don't know if this matters.
Customized DSDT first in OC/ACPI:
While this customized DSDT so far does not enable USB on TB on the MSI (I'm still working on it), it did surprisingly, raise test results as shown below.
The FPS increased from 97 to 142 (previous results here). This is rather significant. Also, the CPU scores increased from 7700 to 8000. All results are bare metal in Big Sur ß6.
One more comment. When going thru the DSDT file, there are many areas where the exact address of the MMIO sections we're using in MmioWhitelist are defined (as shown in Spoiler below for 0xFED00000).
SpoilerMethod (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings { Name (BUF0, ResourceTemplate () { IRQNoFlags () {0} IRQNoFlags () {8} Memory32Fixed (ReadOnly, 0xFED00000, // Address Base 0x00000400, // Address Length ) }) Return (BUF0) /* \HPET._CRS.BUF0 */ }2nd Run:
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5 minutes ago, fabiosun said:
I have this
without any ssdt and only with NV23 Elias firmware
It needs an SSDT for function. NVM23 should still work.
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17 minutes ago, meina222 said:
Yes, I connect to the TB header on the motherboard.
When you start actual testing things don't looks so rosy. I have a TB 3 display (proper not USB-C ) with fully rated TB cable. When I connected the GPU to the TB card with a DP to mini DP bridge cable and then the monitor to TB port, PC won't even boot - BIOS error code 61 (NVRAM initialization). Not sure what this is about but maybe this NVM33 rom is not so nice for me. I enabled above 4G - same issue. I did try to increase memory per port in BIOS for TB - wonder if this is it. Back to DP, boot error is gone.
Wonder if this is related to the Linux firmware error. Maybe the flash was not so good.
I also run a GB beta BIOS. Who knows if Slot 4 is indeed tested. The only way to find out is to reflash back to default and try. Sigh 😞
My understanding is that once firmware is flashed to enable a TB AIC to work in macOS, it will not work in Windows. I would suspect Linux may be a problem too.
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20 minutes ago, fabiosun said:
https://www.amazon.it/gp/product/B010HWCFDA/
I bought this to test
but if I do not achieving your result in ioreg I can't see any choice to have it working
You hardly need to buy anything to test. Just looking at Hackintool will tell you if the USB ports are active.
Marking up meina222's image above (low res so not much detail) as compared to our MSI. When TB-USB is working, the top section, which shows the available USB devices is same for both mobos.
The bottom section, which are the active ports, is populated on the GB mobo by TB USB (XHC5), but is empty on our MSI mobos. The GB mobo properly shows the ports as TypeC+Sw, which are the high speed USB3/C ports.
So the SSDT is properly injecting both TB and USB properties on the GB mobo. The 33 firmware is just fine; don't change it.
We need to study the meina222's GB DDST file to determine what is different from our MSI DDST file with respect to power for USB.
GB mobo:
MSI mobo:
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10 minutes ago, meina222 said:
Might be the NVM33 rom. I don't think the Designare does anything special but who knows. I'm guessing it's the ROM but I have no experience in this area. I may experiment some more and flash back to NVM23 mod to see if Linux likes it better and will share. On the other hand a pretty IOReg is not so worthy without function :).
Edit: FWIW that USB-C does charge my iPhone so not a complete waste 😂
Forgot to say - I also don't connect that TB to internal motherboard header as I only have two USB 2.0 headers. One is taken by the front USB hub of the case, the other by the Bluetooth PCI card I got. So I fished a USB adapter cable like this one https://www.amazon.com/CRJ-9-Pin-Dupont-Header-Single/dp/B07Q4QZW57/ref=sr_1_12?dchild=1&keywords=usb+2.0+adapter+cable+9+pin&qid=1599408979&s=electronics&sr=1-12 to one of my rear USB 2.0 ports. So TB is connected to cable, connected to USB 2.0 port and not internal hub. Not sure if it matters.
Some users have reported that TB header not needed. USB-2 connection and the power connections are optional (the latter for supplying charging, so maybe connecting iPhone not a good idea as it will require over 1A). A better thing to connect to test is a USB-C SSD.
In reading your posts, it said you initially flashed NVM23 and implied you flashed NVM33 over that. I've used NVM33 for Titan Ridge cards. I don't think from tests (I've been involved with CaseySJ's work since he started), that 23 or 33 will adversely affect USB function.
In looking over your DSDT file, it is very similar to the MSI DSDT. I've not yet located anything in it that would suggest a more robust USB response to our SSDTs.
[Discussion] - TRX40 Bare Metal - Vanilla Patches
in General
Posted · Edited by iGPU
That was sometimes seen with 5700XT (and occasionally with Radeon VII) and WEG on the Intel side. If you have WEG enabled, try running with it disabled.
I did notice this esp with USB, if WiFi was enabled. So after checking WEG status, try turning off WiFi (BT being on is okay).