etorix

"Custom" is your key to disabling Secure Boot. PS. In my experience with Xeons, serial ports are no issue at all. macOS is happy to boot with them, and to display "Serial" among networking possibilities. (I haven't dug up my 33.6k modem to check whether they actually work.)

Do we know what this field is, and what are the expected values for those G0xx? Not all conditions can be met simultaneously (G000): If (((G002 != 0x03) && (G000 == One))) { Scope (\_SB.PCI0.GPP7) { Device (UP00) { If (((G002 != 0x03) && (G000 == 0x02))) { Scope (\_SB.PCI0.GPP7) { Device (XH00) so deleting all the conditions create more ACPI objects than would exist if CPVS were properly processed. Possibly more worryingly, there is some debug-like code (calls to M460) and empty stubs If (((G002 != 0x03) && ((G000 == One) && (G002 == 0x04)))){} so there's a risk that the code will further evolve in future BIOS revisions. Maintaing a database of patched DSDTs for successive BIOS versions of boards of interest is going to be cumbersome.

More fundamentally, I wonder why this extra code prevents macOS from booting. Is macOS unable to read the CPVS region and initialise these G0xx variables? Is it a general issue with macOS? A memory mapping issue? An AMD-specific issue?

If I got it right from @Lorys89, this should be it: patched.zip